| By Maureen O'Gara | Article Rating: |
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| February 26, 2008 04:30 PM EST | Reads: |
28,151 |
While AMD stumbles around trying to get its first errata-free Barcelona quads out two years behind Intel, Intel is off planning the launch of its six-core Dunnington microprocessor, a hex, if you will, the last of the expected Core 2-based Xeon server chips before it switches over to the Nehalem microarchitecture capable of supporting eight or more cores. Dunnington, a Bangalore-designed successor to Harpertown, is still supposed to be relatively hush-hush but Intel has reportedly put three dual-core 45nm Penryn chips on a die the size of a postage stamp and sharing a 16MB L3 cache. Like other Penryns, Dunnington still uses a front-side bus.
Dunnington slips into Intel’s Caneland platform and so uses the Clarksboro chipset.
The dingus, which Intel has previously described as pin-compatible with the dual-core/four-socket Tigerton quad, will be two- and four-socket, meaning mainframe-like machines with 24 cores.
Intel is reportedly seeing how quickly it can get the little beast out. It was due before the first of the Nehalem chips and could appear in Q3, maybe even Q2.
Dunnington doesn’t require the record two billion transistors that it takes to make Intel’s next-generation 65nm quad-core Tukwila Itanium, but it’s reportedly close.
Dunnington will appear in a variety of SKUs and a variety of clock rates with power dissipation that ranges beyond 120W.
Meanwhile, on Tuesday Intel introduced Skulltrail, now its eight-core Dual Socket Extreme Desktop Platform for the games market that supports two Intel quads and multi-card graphics from either ATI or Nvidia in a $649 D5400XS board.
Published February 26, 2008 Reads 28,151
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Maureen O'Gara the most read technology reporter for the past 20 years, is the Cloud Computing and Virtualization News Desk editor of SYS-CON Media. She is the publisher of famous "Billygrams" and the editor-in-chief of "Client/Server News" for more than a decade. One of the most respected technology reporters in the business, Maureen can be reached by email at maureen(at)sys-con.com or paperboy(at)g2news.com, and by phone at 516 759-7025. Twitter: @MaureenOGara
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Amit Gurdasani 02/25/08 02:33:14 AM EST | |||
Dunnington succeeds not the two-socket 45 nm LGA 771 Harpertown (meant for the Stoakley platform) but the four-socket 65 nm Socket 604 Tigerton (meant for the Caneland platform), the Xeon MP launched September 6, 2007. Tigerton didn't have a 16 MiB L3 cache, but its predecessor, the 65 nm NetBurst microarchitecture based Tulsa, did. This processor will be interesting to watch. I am especially interested in how it will do on Java application server loads, since those workloads are especially sensitive to the size of the cache. SPECjbb2005 will be the benchmark to watch. |
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